Image Transmission Through Channel Coding Architecture

Section: Research Paper
Published
Sep 1, 2024
Pages
56-64

Abstract

Image transmission in modern communication systems needs fast and low error coding and imperative transmission mechanisms. For engineers, dependable communication over a noisy channel is a long-standing but difficult problem. One of the important types of channel coding is Low-Density Parity-Check (LDPC) codes which are considered Linear Block Codes (LBC). Due to their superior error-correcting ability, LDPC codes are among the most widely used Forward Error Correction (FEC) codes. The purpose of this paper is to create transmitter channel encoder LDPC architectures and the corresponding channel decoder in the receiver for image transmission. The study integrates the Effective Encoding of the LDPC codes algorithm for the encoder and the Bit flipping LDPC codes algorithm for the decoder, Vivado HLS (High_Level Synthesis) is the tool utilized in this work, The HLS loop unrolling optimizing technique is used to give the synthesizer instructions on how to implement a particular code section, the designer can quickly and easily optimize the application, as a result, optimization is done directly on the source code. Additionally, it suggests applying optimization techniques like loop unrolling to every design. C programming language and HLS are used to create all architectures

References

  1. A. V. Bukit and Wirawan, 3D video coding development based on FPGA platform Xilinx Zynq-7000, 2017 International Seminar on Intelligent Technology and Its Applications (ISITIA), Aug. 2017. doi:10.1109/isitia.2017.8124050.
  2. Amer T. Ali and Dhafir A. Alneema, "Design Analysis of Turbo Decoder Based on One MAP Decoder Using High Level Synthesis Tool," Al-Rafidain Engineering Journal (AREJ), vol. 25, pp. 70-77, 2020, doi: 33899/rengj.2020.126801.1022.
  3. Amiri, F. M. Siddiqui, C. Kelly, R. Woods, K. Rafferty, and B. Bardak, "FPGA-Based Soft-Core Processors for Image Processing Applications," Journal of Signal Processing Systems, vol. 87, no. 1, pp. 139156, Apr. 2017, doi: 10.1007/s11265-016-1185-7.
  4. Arwa H. Ashou, and Dhafir A. Alneema, "FPGA Hardware Design of Different LDPC Applications: Survey," Asian Journal of Computer Science Engineering, vol. 6, pp. 35-44, 2021.
  5. Conti, M. Quintana, P. Malagn, and D. Jimnez, "An FPGA Based Tracking Implementation for Parkinsons Patients," Sensors, vol. 20, no. 11, p. 3189, Jun. 2020, doi: 10.3390/s20113189.
  6. Develi and Y. Kabalci, "A comparative simulation study on the performance of LDPC coded communication systems over Weibull fading channels," Journal of Applied Research and Technology, vol. 14, pp. 101-107, 2016, doi: 10.1016/j.jart.2016.04.001.
  7. G. Prasad, C. C. Reddy, and J. C. Babu, "VLSI Implementation of decoding algorithms using EG-LDPC Codes," Procedia computer science, vol. 115, pp. 143-150, 2017, doi: 10.1016 /j.procs.2017.09.119.
  8. Gururaj, Bharathi, and G. N. Sadashivappa. "Channel encoding system for transmitting image over wireless network,"International Journal of Electrical and Computer Engineering, vol.10, 4655, 2020, doi: 10.11591/ijece.v10i5.pp4655-4662.
  9. J. Gaurihar, I. R. Khadse, T. S. Ghonade, A. Borkar, A. Singh, and M. Patil, "Design and implementation of LDPC codes and turbo codes using FPGA," Int. Res. J. Eng. Technol., vol. 3, Issue: 03, pp. 1683-1687, 2016.
  10. J. Gaurihar, I. R. Khadse, T. S. Ghonade, A. Borkar, A. Singh, and M. Patil, "Design and implementation of LDPC codes and turbo codes using FPGA," Int. Res. J. Eng. Technol., vol. 3, pp. 1683-1687, 2016.
  11. M. K. Younis, B. Sh. Mahmood, and F. H. Ali, "Reconfigurable Self-Organizing Neural Network Design and its FPGA Implementation," Al-Rafidain Engineering Journal (AREJ), vol. 17, no. 3, pp. 99115, Jun. 2009, doi: 10.33899/ rengj.2009.42925.
  12. Malin, "High Level Synthesis for ASIC and FPGA," Master's Thesis, Electrical and Information Technology Dept., Lund University, EITM01 20211, 2023.
  13. Marwan Abdulkhaleq Al-yoonus, Saad Ahmed Al-Kazzaz, "FPGA-SoC Based Object Tracking Algorithms: A Literature Review," Al-Rafidain Engineering Journal (AREJ), Volume 28, Issue 2, Page 284-295, September 2023, doi:33899/rengj.2023.138936.1243.
  14. Marzotto, P. Zoratti, D. Bagni, A. Colombari, and V. Murino, "A real-time versatile roadway path extraction and tracking on an FPGA platform," Computer Vision and Image Understanding, vol. 114, no. 11, pp. 11641179, Nov. 2010, doi: 10.1016/j.cviu.2010.03.015.
  15. Murillo, Raul, et al. "Generating Posit-Based Accelerators With High-Level Synthesis,"IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, Issue 10, pp. 4040-4052, October2023, doi: 1109/TCSI.2023.3299009.
  16. N. de Souza and G. L. Nazar, "Cost-effective Resilient FPGA-based LDPC Decoder Architecture," IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 84-89, 01-03 July 2019, doi: 10.1109/IOLTS.2019.8854457.
  17. Nadzri, Muhamad Muzakkir Mohd, and Afandi Ahmad. "SoC FPGA-Based Rapid Prototyping of Compressed, Secured and Wireless Image Transmission for Wildlife Surveillance System,"International Journal of Integrated Engineering, vol.14, pp. 276-285, 2022.
  18. Raju and P. S. Prasad, "Design of an LDPC Decoder and Its Performance," International Journal of Electrical and Electronics Communication, vol. 1, no. 1, 2017.
  19. S. Reddy and V. S. R. Rao, "FPGA Implementation of LDPC Encoder and Decoder using Bit Flipping Algorithm," International Journal of Science and Research, vol. 6, Issue: 9, ,pp. 1683-1690, 2017.
  20. Yasoubi, An efficient hardware implementation of LDPC Decoder, M.S. dissertation, Electrical and Computer Engineering Dept. Concordia University, Montreal, Quebec, Canada, 2020.
  21. Zahraa T. Al-Mokhtar; Farah N. Ibraheem and Hassan F. Al-Layla, A Review of Digital Image Fusion and its Application, Al-Rafidain Engineering Journal (AREJ), Volume 26, Issue 2, Page 309-322, October 2021, doi: 33899/rengj.2021.127928.1055.
Download this PDF file

Statistics

How to Cite

[1]
D. Abdulfattah A. Alneema, ظافر, Z. Ali Alkhayat, and زينب, “Image Transmission Through Channel Coding Architecture”, AREJ, vol. 29, no. 2, pp. 56–64, Sep. 2024.